1. Field of the Invention
The present invention relates to a wait control device for instructing a central processing unit (CPU) to wait for the start of its operation until the device receives a processing completion signal from an external peripheral device.
2. Description of the Prior Art
In a prior wait control device, a memory address space and an input/output (I/O) device space are divided, respectively, and to the divided subspaces wait number are assigned, and further a timing signal indicative of data having been prepared is sent to a bus master with use of a signal fed from a bus slave. The wait control device 1 is disposed in a one-chip microcomputer 2 and is connected to a central processing unit (CPU) 3 and a timer 4, universal asynchronous receiver transmitter (UART) 5, first and second interrupt controllers (IRC) 6a, 6b, refresh controller 7, arbiter 8, and direct memory access controller (DMAC) 9, through an internal bus 2a, as illustrated in FIG. 5.
Referring now to FIGS. 6 and 7, the prior wait control device will be described. Designated at 1 is a wait control resister as the wait control device. The wait control register 1 formed of a wired-logic comprises a space-assigned register 5 in which an address space and an I/O space have previously been assigned by hardware, and a wait number register 6 to set the wait numbers of the above spaces. The space-assigned register 5 has addresses "0000.sub.H " to "1FFF.sub.H " in the memory address space assigned to BLOCK 0 thereof, addresses "2000.sub.H " to "3FFF.sub.H " in the same assigned to BLOCK 1 thereof, addresses "4000.sub.H " to "FFFF.sub.H " in the same assigned to BLOCK 2 thereof, and addresses "00.sub.H " to "FF.sub.H " of the I/O space assigned to BLOCK 3 thereof. The wait number register 6 is formed of 8 bit registers, to which numerals are set to specify the wait numbers of the respective BLOCKs 0 to 3. A table X of FIG. 7 lists the assigned wait numbers for each of the BLOCKs, each number comprising 2 bits for example. For example, in order to assign the wait number of the BLOCK 0 to "2" the WRB0 and WRB1 in the wait number register 6 may be set to "0" and "1", respectively, and in order to assign the wait number of the BLOCK 1 to "1" the WRB2 and WRB3 in the wait number register 6 may be set to "1" and "0", respectively. The wait numbers should be set with enough time compared with processing speeds posssessed by individual external devices. When a CPU takes an access to a memory device such as a ROM, a SRAM, and a DRAM, etc., which have different access times, respectively, it is necessary to set a required number of the wait numbers corresponding to the response times of such memory devices.
In the prior wait control device described above, the address space and the I/O space were divided, and the wait numbers were assigned to respective divided subspaces, and further a timing signal indicative of data being ready was sent to the bus master using a signal fed from the bus slave. Therefore, the bus master and the CPU must keep their waiting states until the signal is fed from the bus slave. This is a very severe when use is made of a low speed I/O and in particular when the I/O has any failure.